A NAND flash memory, being a nonvolatile semiconductor memory, has been used as a file memory, a mobile memory, and further in recent years has been used as a replacement (SSD: Solid State Drive) of HDD of a notebook personal computer. Under such a circumstance, a technique of achieving an increase in memory capacity by three-dimensionally constructing the NAND flash memory, has been developed.
A three-dimensional NAND flash memory which is known at present, is largely divided into a structure that NAND series (channel) is extended horizontally to a surface of a semiconductor substrate (such as VG-NAND: Vertical gate-NAND, S3-FLASH, VSAT: Vertical-stacked array-transistor), and a structure that NAND series is extended vertically to the surface of the semiconductor substrate (such as BiCS-NAND: Bit cost scalable-NAND, P-BiCS-NAND: Pipe shaped bit cost scalable-NAND, TCAT: Tera bit cell array transistor).
A common point of the former structure is that a stacked layer structure of an active area (or control gates) is processed into a line & space pattern, and further the control gates (or the active area) are processed into the line & space pattern formed across the aforementioned stacked layer structure. However, if the number of stacked layers is increased for increasing the memory capacity, there is a problem that processing of the control gates (or the active area) formed across the stacked layer structure is difficult.
Further, a common point of the latter structure is that a hole is formed in the stacked layer structure of the control gates (or an insulating layer), and a column-shaped active area is formed by embedding a semiconductor into the hole. However, BiCS-NAND has a problem that a contact resistance is great between the semiconductor substrate and the active area. Further, in structures of P-BiCS-NAND and TCAT, the stacked layer structure needs to be processed into the line & space pattern, and therefore if the number of stacked layers is increased, the processing thereof is difficult.
Therefore, it is required to provide an architectural concept different from such a conventional three-dimensional NAND flush memory.